1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM), and more particularly to an apparatus and related method for reducing row-shut off time.
2. Description of the Prior Art
A conventional DRAM 10 is shown in FIG. 1 as including an array of memory cells 16 arranged in rows and columns. An individual memory cell 20, shown in FIG. 2, includes an access device, typically a transistor 26, coupled to a capacitor 28. Binary information is stored in memory cell 20 in the form of charge on capacitor 28. If capacitor 28 is charged, a logic level "1" is stored in the memory cell, and, if no charge is present, memory cell 20 stores a logic level "0".
As further shown in FIG. 2, the memory cell is located at the intersection of a word line 24 and data line 22. In particular, word line 24 is connected to the gate of transistor 26, while the drain is conneted to data line 22. In order to read information out of the memory cell, one of a plurality of row decoder circuits 14 (FIG. 1) drives a selected word line 24 high, thereby turning on transistor 26. Charge stored on capacitor 28 then passes from the source to the drain of transistor 26 and onto data line 22, where it is read out by column select circuitry 12 (see FIG. 1).
A word line is provided for each row of memory cells. Accordingly, for relatively large memories (e.g., 4 meg, 16 meg., 64 meg. etc.) a relatively long word line is required to connect to all of the memory cells of a given row. Due to layout considerations, it is frequently necessary to "interleave" the word lines in such arrays, wherein adjacent word lines are respectively serviced by row decoders and drivers positioned on opposite sides of the array.
A particular row decoder circuit, known as a "tree decoder" having a signal associated pull-down transistor for each word line, has been proposed. The tree decoder includes a plurality of series connected MOS transistors, the gates of which respectively receive a row address bit. An MOS transistor connected at one end of the tree decoder has its drain connected to receive a control signal or universal phase signal, and an MOS transistor connected at the other end of the tree decoder has its source connected to an inverter. The output of the inverter is connected to a word line, which is coupled to the drain of a pull-down transistor. The gate of the pull-down transistor is coupled to receive the universal phase signal and the source is connected to ground.
In order to select a particular word line, each of the address lines respectively connected to the gates of the MOS transistors of the tree decoder goes high, thereby rendering each MOS transistor conductive. The universal phase signal coupled to the selected decoder is made low, and this low voltage is passed through the MOS transistors of the tree decoder to the input of the inverter. The inverter then outputs a high voltage to drive the selected word line. At the same time, the low universal phase signal cuts off the pull-down transistor so that the word line is not shorted to ground.
After data has been read out from a memory cell connected to the selected word line, for example, the word line can be deselected by bringing the universal phase signal to a logic level high potential, rendering the pull-down transistor conductive and shorting the word line to ground, and thereby insuring that the output of the inverter is grounded.
In the conventional DRAM, word lines are typically made of polysilicon, which is relatively highly resistive. Thus, relatively large RC delays have been encountered in many DRAMs, requiring a long row turn-on time (i.e., the time to charge the word line up to a voltage that will render transistor 26 conductive), and row shut-off time (i.e., the time required to deselect a word line by discharging to ground). As a result, the overall speed of the DRAM is degraded.
In many applications, a long row turn-on time is not problematic. However, a long row shut-off time can adversely effect operation of the memory. One solution for reducing row-shut off time involves overlaying the polysilicon word line with a metal layer, which periodically contacts the polysilicon word line along its length. While effective in reducing the effective resistance of the word line, this approach is disadvantageous in that it requires additional processing or mask steps, which lengthen the manufacturing process and reduce yields.
The interleaved arrays described above can be fabricated to include shorter word lines having a shorter RC delay and shorter row shut-off times. Since the resistance of the word line is a function of its length, reducing the length of the word line reduces its resistance and, consequently, reduces the RC delay. However, by reducing word line length, additional row decoders are required, which increases chip size, thereby increasing manufacturing cost. Thus, it is desired to improve row shut-off time with no adverse impact on chip size.